This invention relates in general to techniques for fabricating integrated circuits and, more particularly, to a method and apparatus for fabricating self-aligned contacts in an integrated circuit.
Over the last several decades, as the technology of fabricating integrated circuits has matured, one design criteria of progressively increasing importance has been the capability to maximize the amount of circuitry that is implemented within a given area in an integrated circuit. One common component in an integrated circuit is a field effect transistor (FET), which includes spaced source and drain regions in a substrate, a gate section disposed on the substrate at a location centered above the source and drain regions, a dielectric layer which covers the substrate and gate section, spaced contact openings which extend through the dielectric layer to the source and drain regions on opposite sides of the gate section, and electrically conductive contacts within the contact openings. The contact openings are created by etching them through the dielectric layer, at locations determined by a mask which is applied to the dielectric layer. The ability to accurately position the mask relative to the substrate is limited by certain realworld tolerances. Consequently, in a traditional approach, each of the contact openings is spaced outwardly from the gate section a sufficient distance so that, even allowing for tolerance variations in the position of the mask and thus the contact openings, neither of the contact openings will encroach on the gate section.
In order to reduce the area required for implementation of an FET transistor, designs have been developed in which the space between the contact openings is reduced until it is approximately equal to the width of the gate section. However, the same tolerances still exist with respect to placement of the mask used to create these closely-spaced contact openings. Therefore, it is fairly common that at least one of the contact openings will overlap or encroach to some extent on the gate section. These compact transistor designs and the techniques for fabricating them automatically compensate for any misalignment which may occur between the contact openings and the gate section. Therefore, the contacts in these designs are sometimes referred to as xe2x80x9cself-alignedxe2x80x9d contacts.
In a transistor design which uses self-aligned contacts, a focal criteria while etching the source/drain contact openings through the dielectric layer is to ensure that the etching procedure does not etch the gate section in a manner that exposes a surface of a gate electrode within the gate section. This is because, if a surface of the gate electrode is exposed by the contact opening, the conductive contact subsequently created in that contact opening will electrically engage not only the source or drain region, but also the gate electrode, thereby producing a direct short between the gate electrode and the source or drain region. At the same time, contacts to the gate must also be accomplished.
Techniques have been developed to permit fabrication of self-aligned contact openings in a manner which avoids exposing any surface of the gate electrode. These existing approaches have been generally adequate for their intended purposes, but have not been satisfactory in all respects. For example, one approach utilizes the technique of etching a single large contact opening which has respective portions disposed on opposite sides of the gate section. However, this requires one or more steps of planarizing various materials to a level corresponding to an upper end of the gate section, which in turn can place significant physical stresses on the gate section. Other techniques etch two separate contact openings, but involve an approach in which the gate is covered by the point in time where doping and/or silicide formation is to be carried out for the source and drain regions. Consequently, doping and/or silicide formation for the gate section must be separately carried out at an earlier point in time, and this in turn requires not only extra doping or gate resistance reduction steps, but also the use of one or more extra masks.
From the foregoing, it may be appreciated that a need has arisen for a method and apparatus for fabricating self-aligned contacts so as to avoid some or all of the disadvantages of pre-existing approaches. According to the present invention, a method and apparatus are provided to address this need.
More specifically, according to one form of the present invention, a method of making an integrated circuit device involves: fabricating a structure which includes a first section with an upwardly facing first surface portion thereon, and a second section which is adjacent and projects upwardly beyond the first surface portion, the second section having in the region of an upper end thereof an upwardly facing second surface portion, and the first and second surface portions each being provided on material which is one of conductive and semiconductive; forming on the second surface portion a temporary layer; forming on sides of the second section and the temporary layer nearest the first section a side wall portion which is made of a non-conductive material and which projects upwardly beyond the second surface portion; removing the temporary layer; forming a dielectric layer with a top surface spaced substantially above the upper end of the side wall portion; etching the dielectric layer according to a pattern to create a recess portion which extends downwardly within the dielectric layer, the etching step being carried out with a selective etching technique that favors etching of the dielectric material over etching of the material of the side wall portion, wherein at the completion of the etching step a region of the first surface portion is exposed; and filling the recess portion with a conductive material which engages the region of the first surface portion and has on an upper end thereof an upwardly facing surface portion.
According to another form of the present invention, an integrated circuit apparatus includes: structure which includes a first section with an upwardly facing first surface portion thereon, and a second section which is adjacent and projects upwardly beyond the first surface portion, the second section having in the region of an upper end thereof an upwardly facing second surface portion, and the first and second surface portions each being provided on material which is one of conductive and semiconductive; a side wall portion which is disposed on a side of the second section nearest the first section, which is made of a non-conductive material, and which projects upwardly beyond the second surface portion; a non-conductive layer extending over the first and second sections, the non-conductive layer having a top surface spaced substantially above the upper end of the side wall portion, having a further surface on an underside thereof which conforms to the side wall portion and the first and second surface portions, and having therein a recess portion which extends downwardly within the non-conductive layer to a region of the first surface portion; and a portion of conductive material disposed in the recess portion in engagement with the region of the first surface portion, and with an upwardly facing surface portion on an upper end thereof.
According to still another form of the present invention, an integrated circuit apparatus includes: structure having a first section with an upwardly facing first surface portion thereon, and a second section which is adjacent and projects upwardly beyond the first surface portion, the second section having in the region of an upper end thereof an upwardly facing second surface portion, the first and second surface portions each being provided on material which is one of conductive and semiconductive, and the second surface portion having a silicide formed thereon; a side wall portion which is disposed on a side of the second section nearest the first section, which is made of a non-conductive material, and which projects upwardly beyond the second surface portion; a dielectric layer having a top surface spaced substantially above the upper end of the side wall portion, and having therein a recess portion which extends downwardly within the dielectric layer to a region of the first surface portion; and a portion of conductive material disposed in the recess portion in engagement with the region of the first surface portion, and with an upwardly facing surface portion on an upper end thereof.